(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a gate structure for a metal oxide semiconductor field effect transistor (MOSFET), or complimentary metal oxide semiconductor (CMOS), device.
(2) Description of Prior Art
Specific properties of polysilicon, such as the ability to withstand self-aligned metal silicide procedures, have resulted in the extensive use of polysilicon as a material for a gate structure for CMOS devices. However other characteristics of polysilicon can adversely influence the use of polysilicon gate structures for sub-100 um CMOS applications. For example the need to use low operating conditions for present CMOS applications demand devices featuring controllable, low threshold voltage. To establish low threshold voltages the work function of the gate structure should be lower than the work function obtained with a polysilicon gate structure. Doping of the polysilicon gate and of the underlying channel region in the semiconductor can not provide the needed reduced work function, therefore metal gate structures featuring lower work functions are attractive alternatives to polysilicon gate structures for sub-100 um CMOS devices. In addition a polysilicon depletion phenomena, in which the dopant in the polysilicon gate is depleted during subsequent fabrication procedures, also can result in inconsistent gate voltages across the underlying gate insulator layer, again suggesting the use of materials other than polysilicon for gate structures.
Although metal gate structures provide the desired work function and thus allow lower threshold voltages to be realized, several process shortcomings have to be addressed. First, metal gate structures are not compatible with the wet etch procedures used with self-aligned metal silicide applications. Exposure of the metal gate to the silicide procedure can result in degraded gate structures. Secondly the ion implantation masking ability, as well as the ability to withstand the anneal procedures experienced during self-aligned source/drain procedures, of metal gate structures are limited when compared to counterpart gate structures fabricated with polysilicon. Therefore a composite gate structure comprised with a polysilicon top portion needed for implant masking, and comprised with a metal bottom portion needed for work function or threshold voltage purposes, would be desirable.
The procedure needed to define a composite gate structure comprised of polysilicon-metal, is difficult to control in regards to terminating the etch procedure on the gate insulator layer, therefore protecting the underlying source/drain semiconductor material. This present invention will describe a novel procedure for fabrication of a metal containing gate structure, featuring a gate structure definition procedure allowing termination of the procedure at the appearance of the top surface of the underlying gate insulator layer. Prior art, such as Chau et al, in U.S. Pat. No. 5,625,217, Buchanan et al, in U.S. Pat. No. 5,789,312, Lu et al, in U.S. Pat. No. 6,100,188, and Gardner et al, in U.S. Pat. No. 6,326,251, describe methods of fabricating gate structures, but none of these prior art describe the novel gate definition procedure described in the present invention.